Signal peak detection system using sensitized threshold detectors

ABSTRACT

A signal peak detection system is disclosed which in a preferred embodiment utilizes a pair of threshold detectors each having a normally conducting input stage. The initial actuation of one of the detector stages, that is, the cessation of conduction in its input stage, in response to an input analog signal provides threshold information to decision logic for initiating signal analysis processing. Circuit means are provided to remove the &#39;&#39;&#39;&#39;turn-on&#39;&#39;&#39;&#39; bias current from both detector stages coincidentally with the above-mentioned initial actuation. The latter operation &#39;&#39;&#39;&#39;sensitizes&#39;&#39;&#39;&#39; the other detector but the input stage thereof remains conducting due to the slope of the input signal applied thereto. Subsequently, as the input signal passes over-the-peak, only a minimal dv/dt input is necessary to actuate this last detector. The concurrent actuation of both detectors causes a peak indication substantially close to the true signal peak to be presented to the decision logic. An output from the system is generated only when predetermined characteristics of the input signal have been validated by the decision logic.

States atent n manna Primary Examiner- Donald D. Forrer AssistantExaminer-.lohn Zazworsky Attorney-Carl Fissell, Jr.

ABSTRACT: A signal peak detection system is disclosed which in apreferred embodiment utilizes a pair of threshold detectors each havinga normally conducting input stage. The initial actuation of one of thedetector stages, that is, the cessation of conduction in its inputstage, in response to an input analog signal provides thresholdinformation to decision logic for initiating signal analysis processingCircuit means are provided to remove the turn-on" bias current from bothdetector stages coincidentally with the above-mentioned initialactuation. The latter operation sensitizes" the other de tector but theinput stage thereof remains conducting due to the slope of the inputsignal applied thereto. Subsequently, as the input signal passesover-the-peak, only a minimal dv/dt input is necessary to actuate thislast detector. The concurrent actuation of both detectors causes a peakindication substantially close to the true signal peak to be presentedto the decision logic. An output from the system is generated only whenpredetermined characteristics of the input signal have been validated bythe decision logic.

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2 Sheets-Sheet 1 PRHOR RT INVENTOR. RICHARD L. FUSSELL SIGNAL PEAKDETECTION SYSTEM USING SENSITIZED THRESHOLD DETECTORS CROSS REFERENCE TORELATED APPLICATIONS The basic circuit element, a threshold switch,employed in the present invention, as well as the following referenceapplications, is described and claimed in application Ser. No. 679,965,new U.S. Pat. No. 3,546,482, Signal Peak Detection System," by CliffordJ. Bader and Richard L. Fussell. A second copending application Ser. No.68,177 for Sensitive Threshold and Over-the-Peak Signal DetectionSystems," and a third application Ser. No. 76,905 filed Sept. 30, 1970for System for the Detection and Validation of Signal Peaks, both filedin the name of Richard L. Fussell, disclose related detector circuitsand systems. All of the aforementioned applications are assigned to thesame assignee as the present application.

BACKGROUND OF THE INVENTION The invention disclosed herein was made inthe course of, or under a contract with, the Department of the Navy.

The signal peak detection system described and claimed in the referenceSer. No. 679,965 application, comprises a plurality of thresholdswitches which provide an output level transition when the absoluteamplitude of the input signal information begins to decline afterpassing through a maximum value. The second reference application pointsout that while the system described in application Ser. No. 679,965 issuited for a variety of applications, it does not exhibit the capabilityof validating the input signal characteristics as a condition forgenerating an over-the-peak output indication.

In accordance with the present invention and that described in thereference second and third copending applications, circuits andtechniques areprovided which considerably extend and expand the detectorsystem of the reference Ser. No. 679,965 application. The systemdescribed and claimed in the second and third applications, as well asthe system described and claimed herein, provide an optimum hardware andfunctional interface between low-level, long-period analog circuits anddigital decision logic, thereby performing sensitive analog-to-digitalconversion. Moreover, both initial and final information is applied tothe decision logic. The former effects signal analysis processing at anappropriate time before the signal peak occurs, and the latter indicatesa return to the analog steady state condition where no input signal ispresent. The systems described have the capability of limiting thenumber of the decision logic start processings" signals to those whichhave a high probability of satisfying peak detection conditions. Also,the systems provide a direct information constraint to the decisionlogic that the input signal possesses invalid characteristics. Thedigital signal applied to the decision logic is designed to have a fastrise and fall characteristic with minimum noise content, although theanalog signal may be extremely slow and incorporate significantelectrical noise.

The full latch system described in the second copending ap plicationprovides highly efficient peak signal detection suitable for a widevariety of applications. However, in applications where the input signalamplitudes are close to minimum circuit thresholds, the full latchsystem provides an over-thepeak recognition which is considerablyremoved from the true signal peak. The detection systems described'inthe present and the third reference applications are particularly usefulin those special applications where the last-mentioned condition cannotbe tolerated. In performing the peak detection function thesystcmdescribed and claimed herein utilizes a novel approach not taughtin any of the reference applications.

SUMMARY OF THE INVENTION In accordance with a preferred embodiment ofthe present invention, an electrical analog signal is applied bothin-phase and phase-inverted to the respective input terminals of a pairof threshold detectors. Each detector includes an input ourrentamplifying stage which serves as a threshold switch. A sensitizing"current amplifying stage is coupled in common to both detectors. Thestatus of each of the detectors in response to the input signal ismonitored by log'c elements to generate an output peak detection signal.

In operation, the input threshold switch stages of the detectors are ina conducting state in the absence of an input signal. The sensitizing"stage is nonconducting at this time. The DC current biasing the stagesto conduction is derived from the potential on the output electrode ofthe sensitizing" stage, which electrode is coupled to a source of supplypotential by suitable impedance means. An applied signal of suitableamplitude causes a first threshold switching in which one of thethreshold switch stages is driven to nonconduction. It is a key featureof the present invention that the switching of the input stage tononconduction results in the conduction of the sensitizing stage, andthe consequent removal of the tum-on" bias from both detector inputstages. The threshold switch stage of the detector not initiallyactuated, remains conducting due to the polarity of the dv/dt inputsignal. A second threshold switching occurs as the analog signal beginsto decline after passing through its peak. The last-mentioned detectorhaving been sensitized by the removal of the tum-on bias, is driven tononconduction by a minimal dv/dt input of proper polarity. Since thedv/dt of the input signal does not have to overcome the DC bias beforeturning off the sensitized detector, the point of actuation of thedetector is substantially close to the true signal peak. Concurrence ofnonconduction in the detector input stages is recognized as anoccurrence of an over-thepeak condition.

The present system also includes decision logic and means for itsinitiation, whereby the characteristics of the input analog signal areanalyzed and predetermined conditions met prior to the generation of asystem output indicative of a peak condition. The decision logic alsosupplies reset control commands to the threshold detectors on a systemdemand basis.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a schematic diagram of thebasic threshold switch common to the present and the referenceapplications.

FIG. 2, (a--(: illustrate a representative input signal and thewaveforms resulting from the switching action of the threshold detectorstages.

FIG. 3 is a schematic representation of a pair of threshold switchesarranged in a sensitized" configuration.

FIG. 4 is a block diagram of a peak detection system in accordance withthe present invention.

FIG. 5 is a logic diagram for use in providing the decision logic" forthe system of FIG. 4.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The basic circuit element, thethreshold switch, depicted in FIG. 1 is utilized in the presentinvention as well as that of the reference applications. The circuitprovides the capability of generating switching signals at very lowanalog signal amplitudes, for example, less than 10 millivolts peak, andvery low frequencies, less than 0.1 Hz. The current consumed by thebasic switch is less than 5 microamperes. Although the operation of thebasic switch has been described in detail in the reference Ser. No.679,965 application, it is believed helpful at this time to review itscharacteristics.

With reference to FIG. 1, the switching transistor 10 is normally in aconducting state in the absence of an applied analog signal e as aresult of a small DC bias current I The analog signal of interest iscoupled to transistor 10 by way of an ap propriate capacitor Ill andhence in the steady state prior to time T results in no additionalcurrent contribution. That is, the capacitor current i =0 where dv/dt ofthe input signal is also equal to zero. The capacitive coupling alsopermits a generous tolerance for analog steady state voltage conditionsover a wide DC dynamic range. At time t the input voltage starts to gonegative. The switching of transistor 10 occurs only when the analogsignal begins the develop a sufficiently negative dv/dt. Under theseconditions capacitive current, i,.() =C dv/dt occurs and since thecapacitive current is greater than the bias current I the transistorconduction can no longer be sustained and switching commences at time 2The output E of the threshold switch is developed on the collectorelectrode of transistor 10. A knowledge of the transistor parametersdefines a predictable switching point since the device will not turn offinstantaneously when the base current I, becomes zero. This face isillustrated in FIG. 1 by the negative ramp of the input signaltransition voltage AV, which results in a transistor base voltagechange, AV,, in addition to a base current change. As a result, theprecise switching conditions are nt/ 0M and smw) where V is the requireddevice transition voltage for immediate switching. Control of the devicebase transition voltage requirement is best achieved by specifying thetransistor collector-to-emitter saturation voltage which is a readilymeasurably and process-controllable parameter.

It should be noted that for an applied signal positive slope thecapacitor current i,(+)=+C dv/dt merely adds to the bias current Ithereby increasing the transistor base current and maintaining thetransistor in a conducting state. It is therefore apparent that thebasic circuit of FIG. 1 is substantially unresponsive to positive-goinginput signals.

FIGS. 2(a-c) illustrate the signal switching conditions which occur inthe detector configuration of FIG. 3 for a single peak analog signal.FIG. 2a illustrates a typical input signal designated e,,,. The signalcharacteristics may be specified at any given time with reference to theangle 0 which covers 0 to 360", the entire period of the input signal.The waveforms of FIG. 2b illustrate the output voltage levels Th, andTh, occurring during the switching of the respective threshold detectorsin response to e,,,. FIG. 20 depicts the base currents I,,, and I forthe respective threshold switches during the switching conditions ofFIG. 2b.

FIG. 3 illustrates a sensitized detector configuration, utilizing a pairof the basic threshold switches of FIG. 1, comprising transistors 20 and30 and a common sensitizing" stage which includes transistor 40. Asignal inverter dv/dt is also provided. It should be understood that ifthe source itself of the input analog signal provides the push-pulldrive required by the system, the signal inverter is unnecessary and canbe eliminated. If an inverter must be used, numerous varieties of thiscircuit, well known to those skilled in the electronics art,

may be successfully employed. It has been found, for example,

that the use of a stabilized, feedback-type unit gain, invertingamplifier is particularly advantageous because of the inherent lowoutput impedance and stability of such a configuration. The input signale,,, is coupled to the base electrodes of transistors 20 and 30respectively by capacitors l4 and 16. The collector electrodes oftransistors 20 and 30 are coupled respectively to the base electrode oftransistor 40 by resistors 18 and 22. Resistors 24 and 26 provideparallel paths for bias currents I, and I, (each equivalent to I inFIG. 1) to flow from a common point on the collector of transistor 40 tothe respective base electrodes of transistors 20 and 30. The basecurrents for transistors 20 and 30 are designated I,,, and Also includedin the circuit of FIG. 3 are parallel reset current paths comprised ofresistor 28, diode 32, and resistor 34, diode 36 which couple a sourceof reset current respectively to the base electrodes of transistors 20and 30. The output voltages appearing on the collectors of transistors20 and 30 are designated Th, and Th, respectively.

With reference to FIGS. 2a-2c and FIG. 3, the following circuitswitching results will'occur for the analog signal depicted in FIG. 2a.For steady state operation where the input signal angle 0is less than 0,both threshold switch transistors 20 and 30 are conducting. Th, and Th,,the respective outputs of the switches, are substantially at groundpotential. The base electrode of transistor 40 is likewise at groundpotential and the transistor is nonconducting. The voltage on thecollector of transistor 40 at this time approaches that of the source ofthe plus supply potential. Transistors 20 and 30 are biased to theconducting state by currents I, and I, as illustrated in FIG. 20. Alsoat this time, there is no reset control signal present at the RESETterminal.

The first threshold switching occurs as the input signal angle 0proceeds from 0 toward l. At this time, transistors 20 experiences anegative-going input via capacitor 14 and transistor 30 experiences apositive-going input via capacitor 16 by virtue of inverter 12. At pointA in the vicinity of the signal angle, transistor 20 is switched tononconduction by the dr/dt input on its base electrode. The Th, outputrises to approximately the level of the supply potential. As will bedescribed in detail hereinafter in connection with the system of FIG. 4,the switching of transistor 20 and the resultant output signal therefromis utilized to initiate the logic processing of the input signalcharacteristics by the decision logic. Simultaneously with the switchingof transistor 20 a positive-going potential is coupled to the base oftransistor 40 through resistor l8 and the latter transistor is driven toconduction. The voltage on the collector of transistor 40 falls toapproximately ground potential, and the bias currents I, and l, areterminated. This is depicted in FIG. 2c as the sharp negativegoing dropin base currents I,,, and I,,,. Transistor 30 however, remains in itsnormal conducting state by the -hdv/dt base current generated by theinput signal. As indicated in FIG. 2b, Th, remains at a low" level atthis time.

A second threshold switching occurs when 0 is greater than and less than360. At the l80 point, the input signal peak, the threshold switch inputdv/dt conditions reverse and transistor 20 experiences a +dv/dt inputwhile transistor 30 experiences a dv/dt input. At a point B just beyondthe true signal peak, transistor 30 is switched to the nonconductingstate by a minimal -dv/dt input. As noted hereinbefore, the terminationof the tum-on bias currents I, and I, upon the initial actuation oftransistor 20 at point A, eliminates the need for overcoming the bias bythe -dv/dt input and the switching of transistor 30 occurs substantiallyclose to the true signal peak. At this time, both transistors 20 and 30are nonconducting. As will be described in connection with the system ofFIG. 4 the concurrent high" level outputs from both threshold detectorsare indicative of a peak indication and as such will be processed by thedecision logic.

As the input signal angle 0 proceeds toward 360, at point C, the +dv/dtinput on the base of transistor 20 causes I,,, to reach the I, level(FIG. 20) thereby causing transistor 20 to recover, that is, return toits conducting state. This is illustrated in FIG. 2b by the drip inoutput voltage Th, to its original low" level.

The significance of the present invention will become more fullyapparent from a consideration of the complete system implementation ofFIG. 4 in conjunction with the waveforms of FIGS. 2a-2c inclusive.Threshold Detector l and Threshold Detector 2, reference numerals 42 and44 may be each similar to the basic threshold switch of FIG. 1. Thedesignations Th, and Th, represent the outputs from the respectivedetectors 42 and 44. A signal phase inverter 38 provides the push-pulldrive required by the system. FIG. 4 also illustrates a NOR- gate 46 andAND-gate 48, two impedances 50 and 52 providing paths for currents l,and I, respectively, a second inverter 54, and a decision logic block56. The output from NOR-gate 46 is acted upon by inverter 54 and if theoutput of the latter is high it is designated the Y-signal. Theconditions for processing start and sensitize, and reset stop" areindicated to the decision logic by the Y-signal. A high" level outputfrom AND-gate 48 is designated the X-signal and indicates to logic theover-the-peak" condition.

The system conditions for the configuration of FIG. 4 with respect tothe analog signal of FIG. 2a are as follows. Dun'ng steady stateoperation, where the input signal angle 0 is less than 0, the outputsTh, and Th, from detectors 42 and 44 are low." Consequently the inputsto NOR-gate 46 are low" and the output therefrom appearing on line 58 ishigh. This condition provides for the generation of turn-on" biascurrents I, and I, for the detector input threshold switches. Since theinput to inverter 54 is high," its output is low," and there is noY-signal indication to the Decision Logic 56. Likewise there is noX-signal output from AND-gate 46.

With the first threshold switching at point A, with reference to FIGS.2a and 2b, detector 42 is actuated and Th rises to a high" level.Simultaneously, the output of NOR-gate 46 on line 58 drops tosubstantially zero potential, and the bias currents I and I, are removedfrom both detectors. It should be apparent from the foregoing that thesensitizing transistor 40 in FIG. 3 and the NOR-gate 46 of FIG. 4 aresubstantially equivalent in their function of removing the DC bias fromboth detectors upon the initial actuation of one of them. Accordingly,while the embodiments of FIGS. 3 and 4 are included herein as beingpreferred, the present invention should not be considered limited tothem. Other circuits and configurations for performing theaforementioned function may be required in particular applications, andin the light of the teaching found herein will readily suggestthemselves to those skilled in the electronics art.

With the termination of the bias currents I and I at point A, theinverter 54 supplies a Y -signal to decision logic S6 to initiateprocessing of the input analog signal.

At point 13, FIGS. 2b and 2c, just beyond the true signal peak of e asecond threshold switching occurs. Detector 44 is actuated, Th rises toa high level and with both inputs to AND-gate 48 high" at this time, anX-signal is applied to decision logic 56 to indicate the occurrence ofan over-thepeak" condition.

The design of the decision logic 56 will depend upon particularoperating requirements. Depending on the design, a reset control signalwill be applied to both threshold detectors 42 and 44 at a time afterlogic initiation and/or a peak detection recognition. The reset controlwill establish in combination with the input signal, tum-on conditionsfor the detector input stages. The threshold detection output signals'lh and Th will not return to steady state levels until the detectorinput stages (e.g. transistors 20 and 30 of FIG. 3) are fullyconducting, and by this means, the threshold detector outputs accuratelydefine the point at which the reset control signal may be terminated.

FIG. is a logic diagram which may be utilized as the decision logicblock 56 of FIG. 4. It should be understood that the diagram of FIG. 5has been included merely for purposes of example and that the decisionlogic may take numerous forms depending upon the application of thedetector system. The particular form of decision logic to be employedrests with, and is well within the skill of, the logical designer.Accordingly, the present invention should not be considered limited bythe particular design illustrated in FIG. 5.

It is the purpose of the decision logic of FIG. 5 to validate thecharacteristics of the input analog signal prior to generating an outputindicative of an over-the-peak detection. For example, assuming priorknowledge of the frequency and waveform characteristics of the inputsignals expected to be received by the detector system of FIG. 4, theoccurrence of an X-(over-the-peak) signal from AND-gate 48, at a timetoo soon after a Y-(initiate logic) signal from NOR-gate 46, is treatedas an invalid condition and no output over-the-pealt signal is generatedby the detector system. Such invalid condition may result from a varietyof causes, for example, a spurious noise spike superimposed on theanalog signal or an analog signal having a higher frequency that thatacceptable in a particular application -such conditions causing thedecision logic to ignore the presence of the X-signal. The flexibilityof the decision logic design is further emphasized by the last-mentionedsituation where readjustment of the decision logic parameters may bemade to validate such high frequency input signals, if desired.

The processing of the X- and Y-signals by the decision logic of FIG. 5proceeds as follows. In a steady-state condition,

neither X- nor Y-signals are present (the levels on the X- andY-terrninals of FIG. 5 are low"), the flip-flop 66 is in a resetcondition as a result of the "high" voltage level applied to theR-terminal thereof by inverter 62.

It will be assumed for purposes of explanation that the applied analogsignal is that depicted in FIG. 2a, and that in accordance with theoperation of the system of FIG. 4 as described hereinbefore, a Y-signalis applied from NOR-gate 46 to the Y-terminal of the decision logic.This Y-signal is acted upon by the differentiating circuit 64 and theoutput thereof initiates a check period" by triggering a delay mul'tivibrator 66 to provide a predetermined AT. pulse period. The invertedsteady-state signal applied to the R-terminal of flip-flop 60 is alsoremoved at this time. During the AT, period no valid X-signal isanticipated. If an X-signal from AND-gate 44 does appear, it is coupledto the X-t-erminal of the decision logic, and is applied in coincidencewith the positive pulse output of delay multivibrator 66, to ANlD-gate6h. The output from AND-gate 68 is coupled through OR-gate 76 to the S(set) terminal of flip-flop 60. The setting of flip-flop 60 causes areset control signal to be generated by the flip-flop, which signal isapplied in common to the respective reset terminals of the thresholddetectors 42 and 44. The duration of the reset control signal is afunction of the analog signal and the recovery time for the detectorthreshold switch stage. The reset control signal is also applied to asecond delay multivibrator 72 to inhibit its operation. Differentiatingcircuit 74 differentiates the output negative pulse from delaymultivibrator 66 and normally triggers delay multivibrator 72. Howeverin the example under consideration, where an invalid X-signal occurredduring AT the presence of a reset control signal prevents thedifferentiated output of circuit 74 from triggering delay multivibrator72 and initiating a AT; pulse period.

In a second situation, it will be assumed that a Y-initiate logic signalhas occurred and that no X-signal appeared during the first time periodAT,. A negative pulse from delay multivibrator 66 is applied todifferentiating circuit 74 which generates a positive trigger pulsecorresponding in time to the trailing edge of said negative pulse. Thistrigger pulse is applied to delay multivibrator 72 and serves toinitiate a second pulse period AT An X-signal occurring during the ATperiod is regarded as valid.

It will be assumed that an X-signal from AND-gate 46 is applied to theX-terminal of the decision logic during time AT-,,. The X-signal isapplied to AND-gate 76 in coincidence with a positive signal from delaymultivibrator 72. An output signal from AND-gate 76 represents an OUTPUTfrom the detector system indicating that an over-the-peak" condition hasoccurred. Additionally, the AND-gate 76 output effects a setting offlip-flop 70, which in turn results in the reset control signal beingapplied to the reset terminals of threshold detectors 42 and 44, and todelay multivibrator 72, to terminate the pulse period AT If in a thirdsituation, no X-signal occur during the AT, time, the differentiatingcircuit 73 which is operatively connected to receive the negative pulseoutput from delay multivibrator 72 generates a trigger pulsecorresponding in time to the trailing edge of said negative pulse. Thetrigger pulse from differentiating circuit 78 passes through CIR-gate 70and sets flipflop 60, which generates the reset control signal. Thereset control signal is applied to threshold detectors 42 and 44 and ispresent until the analog signal input conditions are such that noY-signals exist. Stated another way, reset control is present until theinput detector stages have resumed their steady state conduction and theTh, and Th outputs of the detectors are both low." With a return tosteady state conditions, inverter 62 of the decision logic returnsflip-flop 60 to the reset state, thereby terminating the reset controlsignal.

The operation of the detection systems described hereinbefore assumedthat a negative-going signal, as in FIG. 2a, was applied to the e inputterminals in FIGS. 3 and 4. It is obvious that the circuit action for apositive-going signal applied to the last-mentioned terminals isidentical except that the behavior of the input threshold switch stagesin each case is interchanged.

It should be apparent from the foregoing description of the inventionand its mode of operation that there is provided a peak signal detectionsignal which although employing a minimal number of components and logicgating, provides peak indications substantially close to the true signalpeak. The system is therefore useful in a wide variety of applicatlons.

It should be understood that changes and modifications of thearrangements described herein may be required to fit particularoperating requirements. These changes and modifications, in so far asthey are not departures from the true scope of the present invention,are intended to be covered by the claims appended hereto.

What is claimed is:

l. A signal peak detection system for receiving an input push-pullelectrical signal comprising first and second threshold detectors eachhaving an input and an output terminal, the in-phase and phase-invertedforms of said input signal being applied respectively to the inputterminals of said threshold detectors, each of said detectors includinga current amplifying stage, a capacitor connecting said input terminalof each detector to its associated current amplifying stage, sensitizingmeans coupled to the output terminals of said detectors and beingresponsive to predetermined signal levels appearing thereon forproviding each of said stages with bias currents of sufficient amplitudeand proper polarity to insure the conduction thereof, each of saidstages being normally in a conducting state in the absence of saidelectrical signal, the degree of conduction of the stages being afunction of the respective instantaneous amplitudes of said in-phase andphase-inverted forms of said electrical signal and the electricalcharges on the capacitors associated therewith, one of said forms ofinput signal initially causing the first detector stage to ceaseconduction, the other of said forms of input signal concurrently causingincreased conduction in the second detector stage and the charging ofits associated capacitor, said sensitizing means terminating the flow ofbias currents to both detector stages in response to the signal levelappearing on the first detector output tenninal as a result of saidcessation of conduction, the conducting state of second detector stagebeing unaffected by the removal of bias current therefrom because of thenature of the electrical signal applied to its input terminal, thepassage of said input electrical signal through its maximum absoluteamplitude resulting in the diminution of conduction in the seconddetector stage and the subsequent discharge of its associated capacitor,whereby said last-mentioned stage is driven to a nonconducting state,both said detector stages being nonconductive at this time, the signallevels appearing respectively on the detector output terminals duringthe coincident nonconduction of the detector stages providing anindication of the occurrence of a peak condition in the input signal.

2. A signal peak detection system as defined in claim 1 furthercharacterized in that each of said current amplifying stages has aninput, an output and a control electrode, each of said capacitors beingconnected between a detector input terminal and the control electrode ofthe amplifying stage associated with that detector, the input electrodesof said stages being connected in common to a source of referencepotential, first and second impedance means for coupling the respectiveoutput electrodes of said stages to a source of supply potential, thirdand fourth impedance means for coupling the respective controlelectrodes of said stages to said sensitizing means, the outputterminals of said pair of threshold detectors corresponding electricallyto the respective output electrodes of said current amplifying stages.

3. A signal peak detection system as defined in claim 2 wherein saidsensitizing means comprises a current amplifying device having an input,an output and a control electrode, the input electrode of said devicebeing connected to said source of reference potential, fifth and sixthimpedance means for coupling the respective output terminals of saiddetectors to the control electrode of said device, a seventh impedancemeans for coupling the output electrode of said device to said source ofsupply potential said third and fourth impedance means coupling therespective control electrodes of said detector stages to the outputelectrode of said device.

4. The signal peak detection system as defined in claim 3 furtherincluding reset means comprising for each of said detectors the seriescombination of a resistor and a diode for coupling the control electrodeof each stage to a source of reset control current.

5. A signal peak detection system as defined in claim 4 wherein saiddetector stages and said current amplifying device are transistors andsaid input, output and control electrodes are respectively, emitter,collector and base electrodes.

6. A signal peak detection system as defined in claim 1 wherein saidsensitizing means comprises a NOR gate having a pair of input terminalsand an output terminal, the output terminals of said detectors beingcoupled to the input terminals of said NOR gate, means coupling theoutput terminal of said NOR gate to said detector stages for providingsaid bias current therefor.

7. A signal peak detection system as defined in claim 6 furtherincluding reset means coupled to said detector stages and adapted to beenergized from a source of reset control current capable of causing saidstages to assume their normally conducting state.

8. A signal peak detection system as defined in claim 7 furtherincluding decision logic means having first and second input terminals,a reset control terminal and a system output terminal, means couplingthe output terminal of said NOR gate to said first decision logic meansinput terminal for selectively initiating processing activity thereinand terminating the generation of reset control current thereby, meansfor coupling said reset control terminal of said decision logic means tosaid reset means, a first AND gate having a pair of input terminals andan output terminal, means coupling said detector output terminalsrespectively to said AND gate input terminals, the signal levelsappearing respectively on said AND gate input terminals during saidcoincident nonconduction of the detector stages allowing said AND gateto provide a peak indication signal to said second decision logic meansinput terminal, said decision logic means providing at said systemoutput tenninal an output signal indicative of a valid detection.

9. A signal peak detection system as defined in claim 8 wherein saiddecision logic means comprises a flip-flop circuit having set and resetterminals, inverter means coupling said first input terminal of saiddecision logic means to the reset terminal of said flip-flop circuits, afirst differentiating circuit coupled to said first decision logic inputterminal, a first delay multivibrator having an input terminal coupledto said first differentiating circuit and a pair of output terminals forproviding outputs of opposite polarity and predetermined duration inresponse to a trigger pulse from said first differentiating circuit,second and third AND gates each having a pair of input terminals and anoutput terminal, an OR gate having first, second and third inputterminals and an output terminal, the output terminal of said OR gatebeing coupled to the set terminal of said flip-flop circuit, meanscoupling said second decision logic input terminal and one of saidoutput terminals of said first delay multivibrator to the respectiveinput terminals of said second AND gate, the output terminals of saidsecond AND gate being coupled to said first input terminal of said ORgate, a second differentiating circuit coupled to the other outputterminals of said first delay multivibrator, a second delaymultivibrator having an input terminal coupled to said seconddifferentiating circuit and a pair of output terminals for providingpulse outputs of opposite polarity and predetermined duration inresponse to a trigger pulse from said second differentiating circuit,means coupling said second decision logic input terminal and one of saidoutput terminals of said second delay multivibrator to the respectiveinput tergate causing said flip-flop circuit to generate a reset controlpulse on said reset control terminal, said reset pulse being appliedconcurrently to said second delay multivibrator to inhibit the operationthereof, and to the reset means of both said threshold detectors.

l i W ii i the equation should read AV; V-

UNITED SIAfiZ-S PA'."E ET OFFICE (IERTIFICATE OF CORRECTION Patent No.3,628,060 Dated December 11?, 1971 Inventor(s) Richard L. Fussell It iscertified that error appears in the above-identified patent and thatsaid Letters Patent are-hereby corrected-as shown below:

On the front page, immediately below 5] Patented Dec. 1 1971" insert[73] Assignee Burroughs Corporation Detroit, Michigan Column 3, line 15,the equation should read -de /dt Z I /C-- column 3 line 16,

r BE(Sw) Column line 13, ":dr/dt" should read edv/dt Column 7, line 5,for "signal" read --system-- Signed and sealed this 30th day of May1972.

(SEAL) Abbe-st:

EI 'JR 'JARQI-LFLETCHERJRQ ROBERT (:OT'I'SCHALK A ates 21mg Office-r.Commissione of Patents

1. A signal peak detection system for receiving an input pushpullelectrical signal comprising first and second threshold detectors eachhaving an input and an output terminal, the inphase and phase-invertedforms of said input signal being applied respectively to the inputterminals of said threshold detectors, each of said detectors includinga current amplifying stage, a capacitor connecting said input terminalof each detector to its associated current amplifying stage, sensitizingmeans coupled to the output terminals of said detectors and beingresponsive to predetermined signal levels appearing thereon forproviding each of said stages with bias currents of sufficient amplitudeand proper polarity to insure the conduction thereof, each of saidstages being normally in a conducting state in the absence of saidelectrical signal, the degree of conduction of the stages being afunction of the respective instantaneous amplitudes of said in-phase andphase-inverted forms of said electrical signal and the electricalcharges on the capacitors associated therewith, one of said forms ofinput signal initially causing the first detector stage to ceaseconduction, the other of said forms of input signal concurrently causingincreased conduction in the second detector stage and the charging ofits associated capacitor, said sensitizing means terminating the flow ofbias currents to both detector stages in response to the signal levelappearing on the first detector output terminal as a result of saidcessation of conduction, the conducting state of the second detectorstage being unaffected by the removal of bias current therefrom becauseof the nature of the electrical signal applied to its input terminal,the passage of said input electrical signal through its maximum absoluteamplitude resulting in the diminution of conduction in the seconddetector stage and the subsequent discharge of its associated capacitor,whereby said last-mentioned stage is driven to a nonconducting state,both said detector stages being nonconductive at this time, the signallevels appearing respectively on the detector output terminals duringthe coincident nonConduction of the detector stages providing anindication of the occurrence of a peak condition in the input signal. 2.A signal peak detection system as defined in claim 1 furthercharacterized in that each of said current amplifying stages has aninput, an output and a control electrode, each of said capacitors beingconnected between a detector input terminal and the control electrode ofthe amplifying stage associated with that detector, the input electrodesof said stages being connected in common to a source of referencepotential, first and second impedance means for coupling the respectiveoutput electrodes of said stages to a source of supply potential, thirdand fourth impedance means for coupling the respective controlelectrodes of said stages to said sensitizing means, the outputterminals of said pair of threshold detectors corresponding electricallyto the respective output electrodes of said current amplifying stages.3. A signal peak detection system as defined in claim 2 wherein saidsensitizing means comprises a current amplifying device having an input,an output and a control electrode, the input electrode of said devicebeing connected to said source of reference potential, fifth and sixthimpedance means for coupling the respective output terminals of saiddetectors to the control electrode of said device, a seventh impedancemeans for coupling the output electrode of said device to said source ofsupply potential, said third and fourth impedance means coupling therespective control electrodes of said detector stages to the outputelectrode of said device.
 4. a signal peak detection system as definedin claim 3 further including reset means comprising for each of saiddetectors the series combination of a resistor and a diode for couplingthe control electrode of each stage to a source of reset controlcurrent.
 5. A signal peak detection system as defined in claim 4 whereinsaid detector stages and said current amplifying device are transistorsand said input, output and control electrodes are respectively emitter,collector and base electrodes.
 6. A signal peak detection system asdefined in claim 1 wherein said sensitizing means comprises a NOR gatehaving a pair of input terminals and an output terminal, the outputterminals of said detectors being coupled to the input terminals of saidNOR gate, means coupling the output terminal of said NOR gate to saiddetector stages for providing said bias currents therefor.
 7. A signalpeak detection system as defined in claim 6 further including resetmeans coupled to said detector stages and adapted to be energized from asource of reset control current capable of causing said stages to assumetheir normally conducting state.
 8. A signal peak detection system asdefined in claim 7 further including decision logic means having firstand second input terminals, a reset control terminal and a system outputterminal, means coupling the output terminal of said NOR gate to saidfirst decision logic means input terminal for selectively initiatingprocessing activity therein and terminating the generation of resetcontrol current thereby, means for coupling said reset control terminalof said decision logic means to said reset means, a first AND gatehaving a pair of input terminals and an output terminal, means couplingsaid detector output terminals respectively to said AND gate inputterminals, the signal levels appearing respectively on said AND gateinput terminals during said coincident nonconduction of the detectorstages allowing said AND gate to provide a peak indication signal tosaid second decision logic means input terminal, said decision logicmeans providing at said system output terminal an output signalindicative of a valid detection.
 9. A signal peak detection system asdefined in claim 8 wherein said decision logic means comprises aflip-flop circuit having set and reset terminals, inverter meanscoupling said first input terminal of said decision logic meanS to thereset terminal of said flip-flop circuit, a first differentiatingcircuit coupled to said first decision logic input terminal, a firstdelay multivibrator having an input terminal coupled to said firstdifferentiating circuit and a pair of output terminals for providingoutputs of opposite polarity and predetermined duration in response to atrigger pulse from said first differentiating circuit, second and thirdAND gates each having a pair of input terminals and an output terminal,an OR gate having first, second and third input terminals and an outputterminal, the output terminal of said OR gate being coupled to the setterminal of said flip-flop circuit, means coupling said second decisionlogic input terminal and one of said output terminals of said firstdelay multivibrator to the respective input terminals of said second ANDgate, the output terminals of said second AND gate being coupled to saidfirst input terminal of said OR gate, a second differentiating circuitcoupled to the other output terminals of said first delay multivibrator,a second delay multivibrator having an input terminal coupled to saidsecond differentiating circuit and a pair of output terminals forproviding pulse outputs of opposite polarity and predetermined durationin response to a trigger pulse from said second differentiating circuit,means coupling said second decision logic input terminal and one of saidoutput terminals of said second delay multivibrator to the respectiveinput terminals of said third AND gate, the output terminal of saidthird AND gate corresponding electrically to said system output terminaland being coupled to said second input terminal of said OR gate, a thirddifferentiating circuit being coupled to said third input terminal ofsaid OR gate, the setting of said flip-flop circuit in response to anoutput signal from said OR gate causing said flip-flop circuit togenerate a reset control pulse on said reset control terminal, saidreset pulse being applied concurrently to said second delaymultivibrator to inhibit the operation thereof, and to the reset meansof both said threshold detectors.